1. Technical Field
The embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor memory device and a method of fabricating the same.
2. Related Art
Semiconductor devices have been highly integrated, and a reduction rate of the semiconductor device has also increased. According to this, when memory devices such as phase-change random access memories (PRAMs), resistive RAMs (ReRAMs), and magnetic RAMs (MRAMs) are fabricated, an access device and a lower electrode are formed in a self-aligned manner.
FIGS. 1 to 4 are views illustrating a method of fabricating a conventional semiconductor memory device and specifically illustrate a method of forming an access device and a lower electrode in a self-aligned manner.
First, as shown in FIG. 1, an access device D, 103 and 105, a first conductive layer 107, and a sacrificial layer 109 are sequentially formed on a semiconductor substrate 101 in which a bottom structure such as a word line (not shown) is formed.
A second conductive layer 111 for reduction of a contact resistance may be further formed between the semiconductor substrate 101 and the access device D. Furthermore, the access device D may include a first type doping layer 103 and a second type doping layer 105. The first type ion doping layer may include a first type positive (+) ion doping layer 103A and a first type negative (−) ion doping layer 103B. The first type ion may be an N type ion and the second type ion may be a P type ion. FIG. 1 shows an example of the access device D.
Each of the first conductive layer 107 and the second conductive layer 111 may have a stacked structure of a titanium (Ti) layer and a titanium nitride (TiN) layer.
The sacrificial layer 109 is used to define a position of a lower electrode to be formed subsequently to the access device when the active device and the lower electrode are formed in a self-aligned manner. The sacrificial layer 109 is formed using a material selected from nitride and materials including nitride.
As shown in FIG. 2, the sacrificial layer 109, the first conductive layer 107, and the access device D are patterned through an exposure and etching process using a mask to expose a surface of the semiconductor substrate 101. When the second conductive layer 111 is formed between the semiconductor layer 101 and the access device D, the second conductive layer 111 is also patterned in the above-described patterning process.
A pillar type structure 113 is formed by the patterning process. Then, a capping layer 115 is formed on the semiconductor substrate including the pillar type structure, an insulating layer 117 for cell separation is formed, and then a planarization process is performed to expose a surface of the sacrificial layer 109.
The capping layer 115 may include a nitride layer or a material layer including nitride. For example, the capping layer 115 may be formed of silicon nitride (Si3N4) or silicon oxynitride (SiON). Furthermore, the insulating layer 117 may be formed using nitride or oxide.
Subsequently, the sacrificial layer 109 is removed to expose the first conductive layer 107 and a process for forming the lower electrode on the first conductive layer 107 is performed.
FIG. 3 shows a cross-sectional view after the sacrificial layer 109 is removed. The sacrificial layer 109 formed of nitride may be removed, for example, using phosphoric acid (H3PO4). At this time, an upper surface and sidewall of the first conductive layer 107 formed below the sacrificial layer 109 may be removed. Thus, the first conductive layer 107 may be thinned in some cells (see A1).
FIG. 4 illustrates a cross-sectional view after a spacer 119 is formed by forming a spacer insulating layer on the semiconductor substrate having a structure as shown in FIG. 3 and then performing a spacer etching process.
In the cell in which the first conductive layer 107 is lost when the sacrificial layer 109 is removed in FIG. 3, the first conductive layer 107 may be further removed due to additional loss in the spacer etching (see A2). Therefore, when a subsequent process of forming the lower electrode is formed, the lower electrode comes in direct contact with the access device D.
Accordingly, a resistance at a contact interface between the access device D and the lower electrode is rapidly increased and this causes a set fail.